This invention relates to a method for making semiconductor light detection devices such as solar cells and photodetectors and products made according to the method. The invention is particularly useful for high-power solar cells and photodetectors. More particularly the invention relates to a method of patterning anti-reflection coatings on solar cells, particularly multi junction solar cells, to accommodate epitaxial contact regions with minimum loss.
Conventional light detection devices have features that reduce the efficiency of optical (e.g. solar) to electrical energy conversion. For example, a portion of the absorbed optical (solar) energy cannot be collected at the electrodes as electrical power and has to be dissipated as heat. For high-power devices, the dissipated heat may result in substantially increased temperature, thereby further reducing the performance of the device. It is desirable to improve efficiency in semiconductor light detection devices and, in particular, solar cell devices.
Conventional multi junction solar cells have been widely used for terrestrial and space applications. Multi junction solar cells, typically considered as high-powered solar cells, comprise multiple diodes (aka junctions) in series connection, realized by growing thin regions of epitaxy in stacks on semiconductor substrates. Each junction in a stack is optimized for absorbing a different portion of the solar spectrum, thereby improving efficiency of solar energy conversion.
Typical fabrication steps in state-of-the-art multi junction solar cell processing have been described by D. Danzilio et al. “Overview of EMCORE's Multi junction Solar Cell Technology and High Volume Manufacturing Capabilities”, CS MANTECH Conference, May 14-17, 2007, Austin, Tex., USA and are summarized below. It should be noted that the list below gives merely the basic steps and that additional process steps may be employed.
1. Epitaxial Growth
2. Mesa Lithography and Etch
3. Metal Grid Lithography Deposition and Lift-off
4. Cap Lithography and Etch
5. Anti-reflection Coating, Deposition, Pattern and Etch
6. Backside Metal Deposition and Anneal
7. Dicing
In the prior art, conventional semiconductor processing techniques are used in the above steps. The process steps between epitaxial growth and dicing (steps 2 through 6) have conventionally not been required to follow a particular order. The Cap Lithography and Etch step together with the Anti-reflection Coating steps of the prior art are relevant to the invention and will be discussed herein for background purposes.
Cap Etch
Typically, the top region in the epitaxial stack (usually called the cap region or cap layer) is a semiconductor region that is highly doped to promote good metal-semiconductor electrical contacts with low contact resistance. The cap region may comprise multiple heterogeneous epitaxial regions. In solar cell manufacturing, the cap region is patterned into a grid of lines (a cap grid) so that in a subsequent metallization step a corresponding metal grid is deposited on top of the cap grid. The patterning and the subsequent cap etch are achieved by conventional semiconductor processing techniques.
FIG. 1 A shows the cross-section schematic of a typical (prior art) semiconductor-based light detection device, represented by a multi junction solar cell 100. The entire device is depicted, but the method according to the invention is performed only on the top and affects only the cap region 3 and the front surface field (FSF) region 4, which are the top regions of a multi-junction epitaxy grown on a semiconductor substrate 5. The solar cell 100 shown in FIG. 1A consists of three sub-cells (junctions) 106-108 that are connected through tunnel junctions 167 and 178. It is to be understood that FIG. 1A is merely an example of a typical multi junction solar cell and that such solar cells may comprise any number of sub-cells. FIG. 1B is a simplified schematic of a typical (prior art) multi junction solar cell which only shows the top epitaxial regions relevant to this patent.
Referring to FIG. 1A, the FSF region 4 is the window region that faces the sun after cap etch. Underneath the FSF region 4 is the emitter region 102 of the top p-n junction 106 that forms a diode. Similar junctions 107 and 108 are disposed below the top p-n junction thus forming a multi junction cell. The FSF region 4 has an important function for the performance in the device. For example, since multi junction solar cells are minority carrier-type devices, the minority carriers generated through photoabsorption in the emitter region 102 of the top junction 106 must diffuse into the depletion region 103 in order to be collected at the base 104. Having a low surface recombination velocity in the emitter region 102 increases the number of minority carriers that make it to the depletion region 103. The function of the FSF region 4 is thus to improve the quality of passivation on the surface region 102 and to reduce the surface recombination velocity by reflecting back the minority carriers that diffuse away from the depletion region 103.
The FSF region 4 is a thin (usually 10 nm to 50 nm) epitaxial region. In addition to improving the collection of the carriers generated in the emitter region 102, the FSF region 4 is usually an absorbing region. The photogenerated minority carriers in the FSF 4 diffuse through the emitter region 102 to the depletion region 103 of the top junction 106 to be collected. Consequently, protection of the top surface 14 of the FSF 4 is important for improving the collection of the minority carriers in the FSF 4.
During conventional manufacturing, the FSF region 4 becomes exposed to a variety of conditions in the process flow subsequent to the cap etch step. These conditions may include, but are not limited to:                Exposure to air and water in a variety of temperature conditions that may occur during process, which can result in oxidation of the FSF region surface 14.        Exposure to metal particles penetrating on the FSF region surface 14.        Contact with various chemicals and photoresist at the FSF region surface 14, potentially leaving residues and damaging the surface.        Partial or full etch of the FSF region 4 due to use of various chemicals in the process steps that follow the cap etch.        
Such adverse conditions reduce the performance of the solar cell substantially. For example in process flows in which the metal grid 2 is deposited while the FSF region 4 is exposed, residual silver or other metals may impinge on, contaminate and permeate into the FSF region 4 and propagate into the inner epitaxial regions 45 thereby reducing efficiency and impacting the performance of solar cells. Consequently, in high-power semiconductor light detection structures, there is a strong need to protect the FSF region surface 14 once it is exposed.
In addition to defects and residues resulting from subsequent photolithography steps, problems are caused by grid metal that comes into direct contact with the FSF region 4. For example, in process flows in which the metal grid 2 is deposited while the FSF 4 is exposed, silver/metal particles may find their way into the exposed FSF and propagate into the p-n junction regions underneath the FSF, rendering the solar cell useless. Moreover, as depicted in FIG. 2, misalignment of the metal grid pattern 2 with respect to the cap grid pattern 3 due to lithographical inaccuracy can result in direct contact between the metal 2 and the FSF 4. The portion of the metal 6 on the FSF 4 may result in metal spikes into the junctions during high temperature process steps, resulting in non-operational devices. Such metal related problems are typically observed as shunted current-voltage (IV) characteristics. FIG. 3 (prior art) compares the IV characteristics of two different solar cells. IV curve 9 is from a high-performance solar cell with no alignment problems, and IV curve 8 shows a shunted current-voltage characteristics resulting from misalignment of the metal grid. In the prior art, to prevent the metal grid from making contact with the FSF, the cap grid width is typically chosen to be larger than the metal grid width for lithographical misalignment tolerance. A wider cap width negatively affects the performance of the solar cell by increasing the shadowing loss and reducing the current that can be extracted. Consequently there is a need to eliminate metal contact with the FSF surface without increasing the shadowing loss.
Anti-Reflection Coating
In prior art multi junction solar cell manufacturing, the cell is coated with an anti-reflection coating (ARC) 1 (FIG. 1) to reduce reflection of sunlight. ARC 1 is usually a stack of thin films of dielectrics, the refractive indices of which are chosen to minimize the reflection of sunlight over a desired wavelength range. The collective ARC 1 region is required to cover the entire surface of the semiconductor facing the sun, i.e., including the FSF. In the past the gridlines were typically also covered during ARC deposition. ARC on busbars must be opened to allow for wirebonding, however. This process step is called contact opening and is typically realized using a separate, additional photolithography step. In the prior art, the ARC deposition and patterning may be performed at different stages and hence there is no specific requirement to realize this step in a particular order within the process flow.